The number of WDT oscillator cycles used for each time-out is shown in Table 4.
23Ģ4 The user can select the start-up time according to typical oscillator start-up. Reset Characteristics Symbol Parameter Min Typ Max Units V POT (Not e:) Power-on Reset Threshold Voltage (rising) V Power-on Reset Threshold Voltage (falling) V V RST RESET Pin Threshold Voltage 0.9 V CC V t TOUT Reset Delay Time-out Period FSTRT Unprogrammed ms t TOUT Note: Reset Delay Time-out Period FSTRT Programmed ms The Power-on Reset will not work unless the supply voltage has been below V POT (falling). Table 3 defines the timing and electrical parameters of the reset circuitry. The circuit diagram in Figure 23 shows the reset logic. If the program never enables an interrupt source, the interrupt vectors are not used and regular program code can be placed at these locations. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine.
During reset, all I/O registers are set to their initial values and the program starts execution from address $000. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V POT ). 1 Features Utilizes the AVR RISC Architecture AVR High-performance and Low-power RISC Architecture 118 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General-purpose Working Registers Up to 8 MIPS Throughput at 8 MHz Data and Nonvolatile Program Memory 8K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles 512 Bytes of SRAM 512 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security Peripheral Features One 8-bit Timer/Counter with Separate Prescaler One 16-bit Timer/Counter with Separate Prescaler Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM On-chip Analog Comparator Programmable Watchdog Timer with On-chip Oscillator Programmable Serial UART Master/Slave SPI Serial Interface Special Microcontroller Features Low-power Idle and Power-down Modes External and Internal Interrupt Sources Specifications Low-power, High-speed CMOS Process Technology Fully Static Operation Power Consumption at 4 MHz, 3V, 25 C Active: 3.0 ma Idle Mode: 1.0 ma Power-down Mode: xxx Reset Sources The AT90S8515 has three sources of reset: Power-on Reset.
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